Manufacturers of semiconductor memory devices continually strive to reduce the size of individual memory cells. By reducing the size of individual memory cells, faster and higher capacity memory devices can be constructed. Conventional memory cells typically comprise a substrate, a transistor formed in the substrate, a storage capacitor coupled to the transistor, and a word line and a bit line for accessing the memory cell. One limiting factor in reducing the size of the memory cell is the size of the access lines of the memory device. In order to resolve this limitation, manufacturers have developed memory devices with word line conductors that extend normal to the substrate. Furthermore, the word lines are narrower than the gate regions of the transistors to which they are coupled. This type of word line is known in the art as an edge-defined word line.
The typical fabrication process of semiconductor memory device comprises a series of lithographic steps where material is either deposited on the device or removed from the device. The minimum dimension of the material which can be deposited or removed is known in the art as the minimum lithographic dimension. In a further attempt to reduce the size of a memory cell, manufacturers have developed word lines which are narrower than the minimum lithographic dimension. The development of sub-lithographic word lines which extend normal to the surface of the substrate has eliminated the size of a word line as a limiting factor in the reduction of the memory cell size. The development, however, has introduced complexities in the other areas of the memory cell.
Traditionally, there are two ways of implementing the capacitor region of a memory cell. A memory cell may contain a trench capacitor or a stacked capacitor. A trench capacitor is formed by etching a hole in the substrate. The storage electrode of the trench capacitor is inside the hole and the plate electrode is the substrate. Because a trench capacitor is located in the substrate of the semiconductor device, it is formed before the word lines of the memory device are formed. Thus, with a trench capacitor, the semiconductor manufacturer can easily form edge-defined word lines on top of the substrate and the trench capacitor.
Trench capacitors have several disadvantages. One disadvantage is the difficulty of fabricating them without introducing silicon crystal defects which result in leakage currents from the storage nodes. In contrast, stacked capacitor are formed on top of the cell transistor and therefore do not significantly affect leakage currents within the silicon. Because of their location, however, spacial interference with the cell wiring may limit the fraction of the cell area available for the capacitor.